工艺流片招标公告（华东光电集成器件研究所2024）
基本信息
发布单位:华东光电集成器件研究所
最终单位:华东光电集成器件研究所
参与方式:公开询价
出价方式:一次性出价
付款方式:
保证金:500.0元
联系人:刘先生
联系方式:13084086982
SMIC 40nm工艺流片技术要求.docx
采购明细
序号
商品名称
品类
采购数量
最少响应量
1
KYWX2024060042-SMIC 40nm工艺流片
外协
1.0批
1.0批
可报价时间
开始时间 2024-07-17 16:21:47
结束时间 2024-07-22 10:00:00
备注： 技术联系人：张工：18913665860
流片技术要求工艺类型：SMIC40nm工艺Metaloption:3P8M_6Ic_2TMc_ALPA2-55℃~125℃工作温度范围；54层mask晶圆数量：12个交期：4个月流片形式：fullmask工艺器件：navt_ckt0.9VNMOS(NGATE-DG-TG-UHVT-LV*PHL-HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)pavt_ckt0.9VPMOS(PGATE-DG-TG-UHVT-LV*PHL-HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)n11ll_ckt1.1VNMOS(NGATE-DG-TG-UHVT-LV-PHL-HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)p11ll_ckt1.1VPMOS(PGATE-DG-TG-UHVT-LV-PHL-HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)nt11ll_ckt1.1VNativeNMOS(NGATE-DG-TG-UHVT-LV-PHL*PSUB-HVT-ULVT-LVT-NC-OVERDR-TGV-DNWTR)nhvt11ll_ckt1.1VHVTNMOS(NGATE-DG-TG-UHVT-LV-PHL*HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)phvt11ll_ckt1.1VHVTPMOS(PGATE-DG-TG-UHVT-LV-PHL*HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)nlvt11ll_ckt1.1VLVTNMOS(NGATE-DG-TG-UHVT-LV-PHL*LVT-ULVT-HVT-PSUB-NC-OVERDR-TGV-DNWTR)plvt11ll_ckt1.1VLVTPMOS(PGATE-DG-TG-UHVT-LV-PHL*LVT-ULVT-HVT-PSUB-NC-OVERDR-TGV-DNWTR)n25ll_ckt2.5VNMOS(NGATE-DG*TG-UHVT-LV-PHL-HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)p25ll_ckt2.5VPMOS(PGATE-DG*TG-UHVT-LV-PHL-HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV-DNWTR)nt25ll_ckt2.5VNativeNMOS(NGATE-DG*TG-UHVT-LV-PHL*PSUB-HVT-LVT-ULVT-NC-OVERDR-TGV-DNWTR)nod33ll_ckt2.5Vod3.3VNMOS(NGATE-DG*TG-UHVT-LV-PHL*OVERDR-HVT-LVT-ULVT-PSUB-NC-TGV-DNWTR)pod33ll_ckt2.5Vod3.3VPMOS(PGATE-DG*TG-UHVT-LV-PHL*OVERDR-HVT-LVT-ULVT-PSUB-NC-TGV-DNWTR)nud18ll_ckt2.5Vud1.8VNMOS(NGATE-DG*TG-UHVT-LV-PHL-OVERDR-HVT-LVT-ULVT-PSUB-NC*TGV-DNWTR)pud18ll_ckt2.5Vud1.8VPMOS(PGATE-DG*TG-UHVT-LV-PHL-OVERDR-HVT-LVT-ULVT-PSUB-NC*TGV-DNWTR)ntod33ll_ckt2.5VodNativeNMOS(NGATE-DG*TG-UHVT-LV-PHL*OVERDR-HVT-LVT-ULVT*PSUB-NC-TGV-DNWTR)navt_dnw_ckt0.9VDNWNMOS(NGATE-DG-TG-UHVT-LV*PHL-HVT-LVT-ULVT-PSUB-NC-OVERDR-TGV*DNW*DNWTR)n11ll_dnw_ckt1.1VDNWNMOS(NGATE-DG-TG-UHVT-LV-PHL-OVERDR-HVT-LVT-ULVT-PSUB-NC-TGV*DNW*DNWTR)nlvt11ll_dnw_ckt1.1VLVTDNWNMOS(NGATE-DG-TG-UHVT-LV-PHL-OVERDR-HVT*LVT-ULVT-PSUB-NC-TGV*DNW*DNWTR)nhvt11ll_dnw_ckt1.1VHVTDNWNMOS(NGATE-DG-TG-UHVT-LV-PHL-OVERDR*HVT-LVT-ULVT-PSUB-NC-TGV*DNW*DNWTR)n25ll_dnw_ckt2.5VDNWNMOS(NGATE-DG*TG-UHVT-LV-PHL-OVERDR-HVT-LVT-ULVT-PSUB-NC-TGV*DNW*DNWTR)nud18ll_dnw_ckt2.5VudDNWNMOS(NGATE-DG*TG-UHVT-LV-PHL-OVERDR-HVT-LVT-ULVT-PSUB-NC*TGV*DNW*DNWTR)nod33ll_dnw_ckt2.5VudDNWNMOS(NGATE-DG*TG-UHVT-LV-PHL*OVERDR-HVT-LVT-ULVT-PSUB-NC-TGV*DNW*DNWTR)pnp11a4ll_ckt1.1VPNP_2*2(DMPNP*AA*SP*NW*SAB-DG-TG*BIPOLA)pnp11a4ll_sba_ckt1.1VPNP_2*2(DMPNP*AA*SP*NW*SAB-DG-TG*BIPOLA)ndio11ll1.1VN+/PWELL(DSTR*AA*SN-DG-TG)pdio11ll1.1VP+/NWELL(DSTR*AA*SP*NW-DG-TG)ndio25ll2.5VN+/PWELL(DSTR*AA*SN-DG*TG)pdio25ll2.5VP+/NWELL(DSTR*AA*SP*NW-DG*TG)parasitic_nwdNWELL/PSUB(DNWTR*NW)parasitic_rwd1.2VRwell/DNW(DNWTR*AA*DNW*NW-DG-TG)parasitic_dnwd1.2VDNW/PWELL(DNWTR*AA*DNW*NW-DG-TG)rndifsab_3t_cktNon-silicideN+Diffusion3T(RESAA*SN*AA*SAB-RESCKT)rpposab_3t_cktNon-silicideP+Poly3T(RESP1*SP*GT*SAB-RESCKT)rppo_3t_cktSilicideP+Poly3T(PLRES*SP*GT-SAB-RESCKT)rnwaa_2t_cktNWELLunderAA(RESNW*NW*AA*SAB*RESCKT)rpposab_2t_cktNon-silicideP+Poly(RESP1*SP*GT*SAB*RESCKT)rppo_2t_cktSilicideP+Poly(PLRES*SP*GT-SAB*RESCKT)rm1_2t_cktMetal1Resistor(M1R*M1-RESP3T)rm2_2t_cktMetal2Resistor(M2R*M2-RESP3T)rm3_2t_cktMetal3Resistor(M3R*M3-RESP3T)rm4_2t_cktMetal4Resistor(M4R*M4-RESP3T)rm5_2t_cktMetal5Resistor(M5R*M5-RESP3T)rtm1_2t_cktTM1Resistor(TM1R*TM1-RESP3T)rutm_2t_cktTM2Resistor(TM2R*MTT2-RESP3T)pvar11ll_ckt1.1VN+/Nwellvaractor(CNGATE-DG-TG*NCAP*VARMOS-DNW)pvar25ll_ckt2.5VN+/Nwellvaractor(CNGATE-DG*TG*NCAP*VARMOS-DNW)dnwpvar25ll_ckt2.5VN+/NwellvaractorwithDNW(CNGATE-DG*TG*NCAP*VARMOS*DNW)dnwnvar25ll_ckt2.5VP+/PwellvaractorwithDNW(CPGATE-DG*TG*PCAP*VARMOS*DNW)mom_3t_cktMtm~MbmMOM(MOMDMY*Mtm~Mbm*Vtm~Vbm-1)mom_2t_cktMtm~MbmMOM(MOMDMY*Mtm~Mbm*Vtm~Vbm-1)dpcnfetpd_cktSRAMPD(NGATE*INST*D2SRAM)dpcnfetwla_cktSRAMPG(NGATE*INST*D2SRAM*SDOP)dpcnfetwlb_cktSRAMPG(NGATE*INST*D2SRAM*SDOP)dpcpfetpu_cktSRAMPU(PGATE*INST*D2SRAM)dslnfetpd_cktSRAMPD(NGATE*INST*DNSRAM-UHVT)dslnfetwl_cktSRAMPG(NGATE*INST*DNSRAM-UHVT*SDOP)dslpfetpu_cktSRAMPU(PGATE*INST*DNSRAM-UHVT)nelvt_ckt_rf0.9VRFNMOS(NGATE-DG-TG*LV-UHVT-HVT-LVT-PSUB-NC-OVERDR-TGV-DGV-DNW*RFDEV*RFMOSD-RFSD)pelvt_ckt_rf0.9VRFPMOS(PGATE-DG-TG*LV-UHVT-HVT-LVT-PSUB-NC-OVERDR-TGV-DGV-DNW*RFDEV*RFMOSD-RFSD)plvt11ll_ckt_rf1.1VRFLV-UHVTTPMOS(PGATE-DG-TG-LV-HVT*LVT-PSUB-NC-OVERDR-TGV-DGV-DNW*RFDEV*RFMOSD-RFSD)n25ll_ckt_rf2.5VRFNMOS(NGATE-DG*TG-LV-UHVT-HVT-LVT-PSUB-NC-OVERDR-TGV-DGV-DNW*RFDEV*RFMOSD-RFSD)dnwlvt11ll_ckt_rf1.1VRFLV-UHVTTDNWMOS(NGATE-DG-TG-LV-HVT*LVT-PSUB-NC-OVERDR-TGV-DGV*DNW*RFDEV*RFMOSD-RFSD)dnw25ll_ckt_rf2.5VRFDNWMOS(NGATE-DG*TG-LV-UHVT-HVT-LVT-PSUB-NC-OVERDR-TGV-DGV*DNW*RFDEV*RFMOSD-RFSD)dnwlvt11ll_ckt_rf_6t1.1V6TRFLV-UHVTTDNWMOS(NGATE-DG-TG-LV-HVT*LVT-PSUB-NC-OVERDR-TGV-DGV*DNW*RFDEV*RFMOSD-RFSD*RFDN6T-RFDN5T)pvar11ll_ckt_rf1.1VMOSFETVaractor(CNGATE-DG-TG*NCAP*VARMOS*RFDEV-DNW-RF3T)dnwpvar11ll_ckt_rf_3t1.1VMOSFETVaractor(CNGATE-DG-TG*NCAP*VARMOS*RFDEV*DNW*RF3T)mom_rfMtm~MbmMOM(MOMDMY-MOM33-MOM50*Mtm~Mbm*Vtm~Vbm-1)rf_ind_2d8alutm_psubspiralinductor(ALPA*MTT2*TM1*M8*M7*M6*M5*M4*M3*M2*M1*RFDEV*INDUMY*PSUB*ALPATXT*MTT2TXT*TM1TXT*M3TXT*M2TXT*M1TXT)ind_2Tdiff_2d8alutm_psub2TDifferentialRFInductor(ALPA*PA*MTT2*TM1*M8*M7*M6*M5*M4*M3*M2*M1*RFDEV*INDUMY*PSUB*MTT2TXT)###NOTINCLUDE(Device:LineNumber)###mom33_2t_ckt:164mom33_3t_ckt:167mom50_2t_ckt:168mom50_3t_ckt:169###ALLDONE###
投标 / 标书制作要点（原创）
本工艺流片涉及「招标公告」，投标方需重点关注：① 营业执照经营范围须含招标公告或对应服务类目；② 提供同类项目业绩证明；③ 报价方案与售后响应须明确；④ 紧盯投标截止与开标节点，建议提前完成标书制作与盖章。当地项目常要求本地化服务能力与快速响应，务必在投标文件中凸显。
标书制作联系冯经理：17551026086
